This invention relates to a bit synchronization circuit. Where a digital communication method is adapted in vehicle communication, for example, a radio paging system, it is important to maintain a synchronization relationship between a transmitter and receiver.
A portable paging receiver carried by a subscriber is not always set in a suitable place for reception, but is sometimes located at the position in which the strength of an electric field received in the portable paging receiver is considerably weakened, for example, by obstacles or standing waves appearing between the portable paging receiver and transmitter. The frequent occurrence of an asynchronous condition between the transmitter and receiver due to intervening obstacles or standing waves, etc. leads to a failure to establish satisfactory communication. Therefore, demand has been made for development of a bit synchronization circuit which, even under adverse conditions, sustains synchronization between the transmitter and receiver and can quickly pull in, that is, restore any asynchronous condition to a synchronous state.
The prior art bit synchronization circuit is classified into a slave type and an independent type. The slave synchronization circuit uses a clock pulse extracted from an input signal by means of a tank circuit or phase-lock loop. The independent synchronization circuit is supplied with an output from a clock pulse oscillator installed in a receiver.
Both types of synchronization circuit are applied to a communication device provided with, for example, a battery-saving system. The numerous receivers of the battery-saving type communication device are divided into an n number of groups. A transmitter repeatedly produces calling signals for the respective groups in series. Receivers belonging to a specified group carry out normal reception while a calling signal for said group is being produced. During the other period, power supply to a radio signal receiver is suspended, thereby saving power consumption.
With the above-mentioned battery-saving type communication device, the radio signal receiver has to be intermittently supplied with power in accordance with a prescribed timing format, even when the supply of a data signal is suspended for long. Where power is intermittently supplied at a different time interval from the prescribed timing format or only for an unduly short length of time, then the radio signal receiver ceases to receive a calling signal.
Where a synchronization circuit is applied to a battery-saving type communication device, the independent synchronization circuit has the following advantages over the slave synchronization circuit: (1) the clock pulse oscillator is operated under stable condition, preventing the occurrence of an asynchronous condition even when a data signal is not supplied for long; (2) time for pull-in is short; and (3) power consumption is small.
However, a bit synchronization circuit used with the prior art independent synchronization system has the drawback that the bit synchronization circuit is liable to be adversely affected, for example, by noises.
There will now be described by reference to FIG. 1 the prior art bit synchronization circuit. A high speed clock pulse oscillator 11 gives forth a high speed clock pulse having a frequency 4f about four times a data rate f. The high speed clock pulse is supplied to the count terminal of a 4-scale ring counter 12 to be counted thereby. The contents of 0 to 3 are shifted in the 4-scale ring counter 12 in the order mentioned.
When the content indicates 0 or 2, the 4-scale ring counter 12 generates an output. When receiving an output denoting the content 0 from the 4-scale ring counter 12 at the reset terminal and an output denoting the content 2 from said counter 12 at the set terminal, then a flip-flop circuit 13 produces a clock pulse.
A digital signal (data rate f) of a base band which has been received and demodulated is conducted to a wave-shaping circuit 14 for correction of the distortion to which the digital signal was subjected during transmission. An output from the wave-shaping circuit 14 is carried to a differential circuit 15 for differentiation. This differential circuit 15 produces a pulse at the point of time at which an output from the wave-shaping circuit 14 has its level shifted, that is, at the rise or fall of said output. An output pulse thus generated is conducted to the reset terminal of the ring counter 12 to reset it.
Even where, with the synchronization circuit of FIG. 1, an input signal to the wave-shaping circuit 14 and an output signal therefrom denoting the content 2 of the ring counter 12 present different phases due to a difference between the frequencies of an output signal from a transmitter (not shown) and an output clock pulse from the clock pulse oscillator 11, the ring counter 12 is reset at the point of time at which an input signal to the wave-shaping circuit 14 has its level shifted, and consequently the phase of an output clock pulse from the clock pulse oscillator 11 is corrected, thereby attaining synchronization between a transmitter and receiver. Further where an input signal ceases to be supplied to the wave-shaping circuit 14, synchronization is still assured between the transmitter and receiver, so long as an output signal from the transmitter and an output clock pulse oscillator 11 indicate a frequency difference falling within a prescribed range.
Where, however, for example, the intensity of an electric field received in a personal pager becomes weaker with a resultant decline in the signal-noise ratio of an input signal supplied to the personal pager, then the point of time at which the input signal has its level shifted occurs at random due to, for example, jitter. As the result, no direct interrelationship is made between the points of time at which the input signal to the personal pager and the output signal from the transmitter have the levels shifted, preventing the ring counter 12 from being reset at definite points of time and leading to a failure to realize synchronization between a transmitter and receiver. As mentioned above, the prior art bit synchronization circuit has the drawback that the circuit is readily affected by atmospheric radio noises, particularly spike noises arising from automobiles.